1. Field of the Invention
The present invention relates to a multilayer capacitor and, more particularly, to a multilayer capacitor which can be advantageously used in high frequency circuits.
2. Description of the Related Art
Conventional multilayer capacitors include that described in Japanese Unexamined Patent Publication No. H2-256216 in which a multilayer capacitor 1, as shown in FIGS. 15 through 17, is disclosed. FIG. 15 is a plan view of the external appearance of the multilayer capacitor 1. FIG. 16 is a plan view of a first section of the multilayer capacitor 1 showing a first electrode 10 located on one surface of one internal dielectric layer 9 of the capacitor 1. FIG. 17 is a plan view of a second section of the multilayer capacitor 1 showing a second electrode 11 located on one surface of a differential internal dielectric layer 9 of the capacitor 1.
Referring to FIGS. 15-17, the multilayer capacitor 1 includes a capacitor main body 8 in the form of a rectangular parallelpiped having two principal surfaces 2 and 3 in a face-to-face relationship with each other and four side surfaces 4, 5, 6 and 7 connecting the principal surfaces 2 and 3. The capacitor main body 8 includes a plurality of dielectric layers 9 (FIGS. 16-17) made of, for example, a ceramic dielectric material. Each of the dielectrical layers is generally planar in shape and lies generally parallel to the principal surfaces 2 and 3. At least a pair of first and second internal electrodes 10 and 11 are provided on respective surfaces of the dielectric layers 9 in a face-to-face relationship with each other with a dielectric layer 9 interposed therebetween to form a capacitor unit.
The first internal electrode 10 is formed with four lead electrodes 12, 13, 14 and 15 which extend to two opposing side surfaces 4 and 6, as shown.
Each lead electrode 12, 13, 14 and 15 is coupled to a respective external terminal electrode 16, 17, 18 and 19 provided on the side surfaces 4 and 6 or the capacitor main body 8. Specifically, the lead electrodes 12 and 13 are connected to the external terminal electrodes 16 and 17, respectively, which are located on the side surface 4, and the lead electrodes 14 and 15 are connected to the external terminal electrodes 18 and 19, respectively, which are located on the side surface 6.
Referring to FIG. 17, the second internal electrode 11 is also formed with four lead electrodes 20, 21, 22 and 23 which extend to the side surfaces 4 and 6, respectively. More specifically, the lead electrodes 20 and 21 extend to positions on the side surface 4 which are different from the positions to which the lead electrodes 12 and 13 extend, and the lead electrodes 22 and 23 extend to positions on the side surface 6 of the main body 8 which are different from the positions to which the lead electrodes 14 and 15 extend.
The lead electrodes 20 through 23 are electrically coupled to external terminal electrodes 24, 25, 26 and 27, respectively. External terminal electrodes 24 and 25 are located on the side surface 4 at positions which are different from those of the external terminal electrodes 16 and 17. External terminal electrodes 26 and 27 are located on the side surface 6 at positions which are different from the positions of the external terminal electrodes 18 and 19.
Thus, the plurality of first external terminal electrodes 16 through 19 and the plurality of second external terminal electrodes 24 through 27 are arranged on the two side surfaces 4 and 6 such that they alternate adjacently to each other.
FIG. 18 illustrates current flowing through the multilayer capacitor 1 as viewed in plan view corresponding to FIG. 17. In FIG. 18, first internal electrode 10 and second internal electrode 11, shown with broken and solid lines, respectively, are shown in an overlapping relationship.
In FIG. 18, the arrows indicate typical current paths and directions. In the state illustrated, current flows from each of the external terminal electrodes 24 through 27 to each of the external terminal electrodes 16 through 19. Because an alternating current is used, the direction of current flow will reverse periodically.
When the currents flow, magnetic flux is induced. The direction of the flux is determined by the direction of the currents to produce self-inductance components. Since the currents flow in various directions at central regions 28 (indicated by circles) of the internal electrodes 10 and 11, the induced magnetic flux generated by the various currents is canceled and substantially no net magnetic flux is produced in those regions.
The current in the vicinity of each of the external terminal electrodes 16 through 19 and 24 through 27 tends to flow toward each of the external terminal electrodes 16 through 19 and away from each of the external terminal electrodes 24 through 27. There are currents that flow to the left and right as viewed in FIG. 18 to spread at an angle of about 180 degrees. As a result, a major part of magnetic flux is canceled and there is no significant generation of net magnetic flux in these areas.
Therefore, in the multilayer capacitor 1 shown in FIGS. 15 through 17, the generation of self-inductance is suppressed in the areas points described above to reduce equivalent series induction (hereinafter xe2x80x9cESLxe2x80x9d).
However, currents flow substantially in the same direction in the vicinity of each of the side surfaces 5 and 7 on which no external terminal electrodes are provided, i.e., at each of the left and right edge portions indicated by hatching in FIG. 18. This results in substantially no cancellation of magnetic flux in these areas and significant net self-inductance is created. Therefore, the measures taken to reduce ESL in the multilayer capacitor 1 shown in FIGS. 15 through 17 is less than desirable.
It is therefore an object of the invention to provide a multilayer capacitor which more effectively reduces ESL.
In accordance with one aspect of the present invention, a multilayer capacitor, comprises:
a capacitor main body having a generally rectangular parallelpiped shape with two principal surfaces in a face-to-face relationship with each other and four side surfaces connecting said principal surfaces;
m capacitor units formed in said capacitor main body, m being an integer greater than or equal to one, each of said capacitor units being formed by a respective pair of first and second internal electrodes disposed in said main body in a face-to-face relationship with a dielectric material layer interposed therebetween to form a capacitor unit;
n first external electrodes, n being an integer greater than 2, each of said first external electrodes being located on a respective one of said side surfaces of said capacitor main body, at least one of said first external electrodes being located on each of at least three of said side surfaces;
said first internal electrode having n first lead electrodes, each of said first lead electrodes extending to and being electrically coupled to a respective one of said first external electrodes;
p second external electrodes, p being an integer greater than 1, each of said second external electrodes being located on a respective one of said side surfaces of said capacitor main body; and
said second internal electrode having p second lead electrodes, each of said second lead electrodes extending to and being electrically coupled to a respective one of said second external electrodes.
The internal and lead electrodes are preferably arranged in such a manner that when currents of different polarity are applied to said first and second internal electrodes, the net induced inductance in the area of all four of said side surfaces is substantially zero.
In one embodiment of the present invention, the first internal electrode is formed with at least four first lead electrodes which extend respectively to respective ones of the four side surfaces. An equal number of first external terminal electrodes are provided. At least one of the first external terminal electrodes is located on each of the four side surfaces.
In this embodiment, the second internal electrode is formed with at least four second lead electrodes which extend to respective ones of the four side surfaces. An equal number of second external terminal electrodes are provided. At least one of the external terminal electrodes is located on each of the four side surfaces.
It is more advantageous if the above-described configuration is employed for both of the first and second internal electrodes.
In another embodiment, for each side surface which has both a first and a second external terminal electrode, each of the first external terminal electrodes located on that surface is located adjacent to one a corresponding second external terminal electrode located on that side surface. It is more advantageous if all of the first external terminal electrodes and all of the second external terminal electrodes are arranged such that they alternate with each other throughout the four side surfaces.
In yet another embodiment, all of the external terminal electrodes are arranged such that they are not adjacent to any other external electrode which is connected to the same internal electrode.
In still another embodiment, the first external internal electrode is formed with three first lead electrodes which extend respectively to three of the side surfaces. The second internal electrode is formed with two second lead electrodes which extend respectively to two of the side surfaces, one of which does have a first external electrode.
In the most preferred embodiment, at least one of the first and at least one of the second external terminal electrodes is provided on each of the four side surfaces.
A plurality of capacitor units can be provided in the multilayer capacitor. Each capacitor unit includes a respective pair of first and second internal electrodes with a respective dielectric layer located therebetween.
According to the present invention, the effect of reducing ESL can be expected from effective cancellation of magnetic and reduction of the lengths of currents achieved by providing a third internal electrode facing at least either the first or second internal electrodes with a dielectric material layer interposed therebetween. The third internal electrode is formed with at least two third lead electrodes which extend to respective ones of the side surfaces. An equal number of third external terminal electrodes are provided on the corresponding side surfaces and are electrically coupled to respective ones of the third lead electrode.
In the above-described embodiment, when all of the first, second and third external terminal electrodes are arranged in the same order of arrangement repeated throughout the four side surfaces, the various components of magnetic flux can be more effectively canceled and the lengths of the current paths can be shortened further for a further reduction of ESL.